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FPL
2004
Springer
205views Hardware» more  FPL 2004»
16 years 3 days ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
IWMM
2004
Springer
101views Hardware» more  IWMM 2004»
16 years 2 days ago
Exploring the barrier to entry: incremental generational garbage collection for Haskell
We document the design and implementation of a “production” incremental garbage collector for GHC 6.2. It builds on our earlier work (Non-stop Haskell) that exploited GHC’s ...
Andrew M. Cheadle, A. J. Field, Simon Marlow, Simo...
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
15 years 12 months ago
Architecting Millisecond Test Solutions for Wireless Phone RFIC's
Today’s low cost wireless phones have driven a need to be able to economically test high volumes of complex RF IC’s at a fraction of the cost of the IC. In June of 2001 the IB...
John Ferrario, Randy Wolf, Steve Moss
184
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ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 11 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
15 years 11 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah