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» Designing and Implementing Malicious Hardware
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ASPDAC
2008
ACM
134views Hardware» more  ASPDAC 2008»
15 years 8 months ago
Automatic re-coding of reference code into structured and analyzable SoC models
The quality of the input system model has a direct bearing on the effectiveness of the system exploration and synthesis tools. Given a well-structured system model, tools today are...
Pramod Chandraiah, Rainer Dömer
IESS
2009
Springer
182views Hardware» more  IESS 2009»
15 years 4 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
16 years 3 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
16 years 10 days ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
ISQED
2005
IEEE
84views Hardware» more  ISQED 2005»
16 years 9 days ago
Performance Driven OPC for Mask Cost Reduction
With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an inte...
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, J...