2945 search results - page 306 / 589 » Designing and Implementing Malicious Hardware |
165
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FPL
2007
Springer
16 years 26 days ago
2007
Springer
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
161
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
137
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ASAP
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
219
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ARC
2008
Springer
15 years 8 months ago
2008
Springer
Abstract. Financial applications are one of many fields where a multivariate Gaussian random number generator plays a key role in performing computationally extensive simulations. ...
156
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CAL
2006
15 years 6 months ago
2006
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...