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FPGA
2009
ACM
273views FPGA» more  FPGA 2009»
16 years 1 months ago
A parallel/vectorized double-precision exponential core to accelerate computational science applications
Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e−x in computer simulation experiments. While it is common to ...
Robin Pottathuparambil, Ron Sass
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
16 years 1 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...
ASPLOS
2006
ACM
16 years 21 days ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
16 years 3 months ago
A high-performance parallel CAVLC encoder on a fine-grained many-core system
—This paper presents a high-performance parallel context-based adaptive length coding (CAVLC) encoder implemented on a fine-grained many-core system. The software encoder is desi...
Zhibin Xiao, Bevan Baas
ARITH
2009
IEEE
16 years 1 months ago
Fully Redundant Decimal Arithmetic
Hardware implementation of all the basic radix-10 arithmetic operations is evolving as a new trend in the design and implementation of general purpose digital processors. Redundan...
Saeid Gorgin, Ghassem Jaberipur