2945 search results - page 297 / 589 » Designing and Implementing Malicious Hardware |
174
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ITC
2003
IEEE
16 years 3 hour ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
174
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ITC
2003
IEEE
16 years 2 hour ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
224
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
144
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ASAP
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
137
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators...