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» Designing and Implementing Malicious Hardware
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ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
16 years 11 days ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
CODES
1999
IEEE
15 years 11 months ago
Software controlled power management
Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Pow...
Yung-Hsiang Lu, Tajana Simunic, Giovanni De Michel...
AHS
2007
IEEE
211views Hardware» more  AHS 2007»
15 years 10 months ago
Synthesis of Multimode digital signal processing systems
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
Caaliph Andriamisaina, Emmanuel Casseau, Philippe ...
CDES
2006
101views Hardware» more  CDES 2006»
15 years 8 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
16 years 1 months ago
Using functional independence conditions to optimize the performance of latency-insensitive systems
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
Cheng-Hong Li, Luca P. Carloni