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AHS
2007
IEEE
252views Hardware» more  AHS 2007»
16 years 1 months ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
16 years 11 days ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
FPGA
2010
ACM
197views FPGA» more  FPGA 2010»
15 years 10 months ago
A 3d-audio reconfigurable processor
Various multimedia communication systems based on 3DAudio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in t...
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi G...
IJES
2008
130views more  IJES 2008»
15 years 6 months ago
Deriving efficient control in Process Networks with Compaan/Laura
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...
MAM
2006
95views more  MAM 2006»
15 years 6 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek