2945 search results - page 283 / 589 » Designing and Implementing Malicious Hardware |
159
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DATE
2006
IEEE
16 years 24 days ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
165
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ASYNC
2005
IEEE
16 years 11 days ago
2005
IEEE
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
243
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FPT
2005
IEEE
16 years 11 days ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
184
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FPGA
2005
ACM
16 years 8 days ago
2005
ACM
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
149
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ICES
2001
Springer
15 years 11 months ago
2001
Springer
Abstract. Embryonics is a long-term research project attempting to draw inspiration from the biological process of ontogeny, to implement novel digital computing machines endowed w...