2945 search results - page 273 / 589 » Designing and Implementing Malicious Hardware |
183
Voted
CODES
2007
IEEE
16 years 1 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
172
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ISCAS
2003
IEEE
16 years 17 hour ago
2003
IEEE
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...
162
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ACSD
2006
IEEE
15 years 8 months ago
2006
IEEE
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
197
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BIRTHDAY
2012
Springer
14 years 2 months ago
2012
Springer
We propose a new countermeasure to protect block ciphers implemented in leaking devices, at the intersection between One-Time Programs and Boolean masking schemes. First, we show t...
196
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FPGA
2005
ACM
16 years 8 days ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...