2945 search results - page 262 / 589 » Designing and Implementing Malicious Hardware |
187
click to vote
DDECS
2009
IEEE
16 years 1 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
129
click to vote
DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 µm Bipolar CMOS DMOS (BCD) technology. The pr...
179
click to vote
SBACPAD
2007
IEEE
16 years 1 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
168
click to vote
ISQED
2006
IEEE
16 years 22 days ago
2006
IEEE
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
143
click to vote
ACSD
2005
IEEE
16 years 10 days ago
2005
IEEE
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...