2945 search results - page 259 / 589 » Designing and Implementing Malicious Hardware |
156
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ICCAD
1996
IEEE
15 years 11 months ago
1996
IEEE
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
151
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
108
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
We extend the Surfliner on-chip distortionless transmission line scheme and provide more details for the implementation issues. Surfliner seeks to approach distortionless transmiss...
165
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ASYNC
2004
IEEE
15 years 10 months ago
2004
IEEE
De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronizatio...
184
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ISSS
1995
IEEE
15 years 10 months ago
1995
IEEE
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...