Sciweavers

2945 search results - page 238 / 589
» Designing and Implementing Malicious Hardware
Sort
View
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
16 years 1 months ago
Timing simulation of interconnected AUTOSAR software-components
AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-t...
Matthias Krause, Oliver Bringmann, André He...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
16 years 1 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
FCCM
2007
IEEE
146views VLSI» more  FCCM 2007»
16 years 1 months ago
Mitrion-C Application Development on SGI Altix 350/RC100
This paper provides an evaluation of SGI® RASC™ RC100 technology from a computational science software developer’s perspective. A brute force implementation of a two-point an...
Volodymyr V. Kindratenko, Robert J. Brunner, Adam ...
FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 10 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...