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ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
16 years 7 days ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ACMACE
2005
ACM
16 years 6 days ago
Designing a narrative-based audio only 3D game engine
Immersing players in believable and engaging virtual environments is a common goal for many interactive computer games. While PC-based audio only games set in virtual worlds have ...
Timothy Roden, Ian Parberry
189
Voted
IEEEPACT
2003
IEEE
15 years 12 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
HPCA
1996
IEEE
15 years 10 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
DSN
2011
IEEE
14 years 6 months ago
Resource and virtualization costs up in the cloud: Models and design choices
—Virtualization offers the potential for cost-effective service provisioning. For service providers who make significant investments in new virtualized data centers in support of...
Daniel Gmach, Jerry Rolia, Ludmila Cherkasova