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FPL
2005
Springer
149views Hardware» more  FPL 2005»
16 years 5 days ago
Heterogeneity Exploration for Multiple 2D Filter Designs
Many image processing applications require fast convolution of an image with a set of large 2D filters. Field - Programmable Gate Arrays (FPGAs) are often used to achieve this go...
Christos-Savvas Bouganis, Peter Y. K. Cheung, Geor...
CODES
2003
IEEE
15 years 12 months ago
Design optimization of mixed time/event-triggered distributed embedded systems
Distributed embedded systems implemented with mixed, eventtriggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases...
Traian Pop, Petru Eles, Zebo Peng
BWCCA
2010
15 years 1 months ago
Advanced Design Issues for OASIS Network-on-Chip Architecture
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...
Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, K...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
16 years 2 days ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
MICRO
2008
IEEE
92views Hardware» more  MICRO 2008»
16 years 1 months ago
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...
Kypros Constantinides, Onur Mutlu, Todd M. Austin