2945 search results - page 222 / 589 » Designing and Implementing Malicious Hardware |
165
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ASYNC
2003
IEEE
15 years 12 months ago
2003
IEEE
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...
153
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FPL
2001
Springer
15 years 11 months ago
2001
Springer
Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image pr...
167
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
140
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ITC
2003
IEEE
15 years 12 months ago
2003
IEEE
The IEEE 1149.6 standard was approved in March of 2003. The standard extends the capability of the IEEE 1149.1 standard to include AC-coupled and/or differential nets. These nets ...
133
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ASYNC
2000
IEEE
15 years 11 months ago
2000
IEEE
This paper presents several new asynchronous FIFO designs. While most existing FIFO’s trade higher throughput for higher latency, our goal is to achieve very low latency while m...