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» Designing and Implementing Malicious Hardware
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CDES
2010
184views Hardware» more  CDES 2010»
15 years 4 months ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
TVCG
2012
186views Hardware» more  TVCG 2012»
13 years 9 months ago
Topology Verification for Isosurface Extraction
—The broad goals of verifiable visualization rely on correct algorithmic implementations. We extend a framework for verification of isosurfacing implementations to check topologi...
Tiago Etiene, Luis Gustavo Nonato, Carlos Eduardo ...
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
16 years 3 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
EH
2000
IEEE
156views Hardware» more  EH 2000»
15 years 11 months ago
Evolution of Analog Circuits on Field Programmable Transistor Arrays
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
Adrian Stoica, Didier Keymeulen, Ricardo Salem Zeb...
IEEEPACT
2003
IEEE
15 years 12 months ago
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
María Jesús Garzarán, Milos P...