Sciweavers

2945 search results - page 196 / 589
» Designing and Implementing Malicious Hardware
Sort
View
MSE
2002
IEEE
153views Hardware» more  MSE 2002»
15 years 11 months ago
A Framework for User Interface Design in Visual Information Retrieval
This paper describes the user interface framework of the VizIR project ([4]). VizIR is an open project to develop a Java-based, extendible and well-documented asset framework for ...
Horst Eidenberger, Christian Breiteneder
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 11 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 10 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
ISCAS
1994
IEEE
117views Hardware» more  ISCAS 1994»
15 years 10 months ago
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy
This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and p...
Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
FPL
2006
Springer
125views Hardware» more  FPL 2006»
15 years 10 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt