2945 search results - page 193 / 589 » Designing and Implementing Malicious Hardware |
174
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IPPS
2005
IEEE
16 years 5 days ago
2005
IEEE
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
154
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ISPD
1999
ACM
15 years 11 months ago
1999
ACM
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
157
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
171
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FPL
2000
Springer
15 years 10 months ago
2000
Springer
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better...
167
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ASAP
2007
IEEE
15 years 8 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...