Sciweavers

2945 search results - page 191 / 589
» Designing and Implementing Malicious Hardware
Sort
View
IPPS
1998
IEEE
15 years 10 months ago
BIP: A New Protocol Designed for High Performance Networking on Myrinet
Abstract. High speed networks are now providing incredible performances. Software evolution is slow and the old protocol stacks are no longer adequate for these kind of communicati...
Loïc Prylli, Bernard Tourancheau
ASAP
2004
IEEE
115views Hardware» more  ASAP 2004»
15 years 10 months ago
Design of the QBIC Wearable Computing Platform
Wearable computing systems can be broadly defined as mobile electronic devices that can be unobtrusively embedded in a user's outfit as part of the garment or an accessory. U...
Oliver Amft, Michael Lauffer, Stijn Ossevoort, Fab...
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
15 years 10 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn
CODES
2007
IEEE
16 years 28 days ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
16 years 6 days ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...