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ASPDAC
2004
ACM
89views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Predictable design of low power systems by pre-implementation estimation and optimization
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
Wolfgang Nebel
DAC
2005
ACM
16 years 7 months ago
A lattice-based framework for the classification and design of asynchronous pipelines
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Peggy B. McGee, Steven M. Nowick
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
15 years 11 months ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 12 months ago
RTOS Modeling for System Level Design
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
Andreas Gerstlauer, Haobo Yu, Daniel Gajski
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...