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» Designing and Implementing Malicious Hardware
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FPL
2010
Springer
139views Hardware» more  FPL 2010»
15 years 4 months ago
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
MSE
2003
IEEE
101views Hardware» more  MSE 2003»
15 years 12 months ago
Internet-based Tool for System-On-Chip Project Testing and Grading
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
Christopher K. Zuver, Christopher E. Neely, John W...
MICRO
1992
IEEE
99views Hardware» more  MICRO 1992»
15 years 10 months ago
An investigation of the performance of various dynamic scheduling techniques
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
Michael Butler, Yale N. Patt
ICCAD
1995
IEEE
114views Hardware» more  ICCAD 1995»
15 years 10 months ago
Sequential synthesis using S1S
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
16 years 19 days ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer