2945 search results - page 169 / 589 » Designing and Implementing Malicious Hardware |
188
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RSP
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we propose the novel concept of probabilistic design for multimedia systems and a methodology to quickly explore such design space at an early design stage. The pro...
187
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ICCAD
2007
IEEE
16 years 3 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
155
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
147
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VLSID
2002
IEEE
16 years 7 months ago
2002
IEEE
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
152
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CHES
2001
Springer
15 years 11 months ago
2001
Springer
This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and t...