2945 search results - page 160 / 589 » Designing and Implementing Malicious Hardware |
151
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DDECS
2007
IEEE
15 years 8 months ago
2007
IEEE
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...
133
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ISCAS
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents a monolithic implementation of a cryptosystem based on the Corron and Hahs scheme [I]. The baseband chaotic encryptioddecryption system has been designed at th...
171
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FCCM
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
167
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
154
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ASYNC
2002
IEEE
15 years 11 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...