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SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
16 years 24 days ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
16 years 17 days ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
16 years 4 days ago
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
16 years 4 days ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 11 months ago
A Top-Down Microsystems Design Methodology and Associated Challenges
An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodo...
Michael S. McCorquodale, Fadi H. Gebara, Keith L. ...