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DELTA
2006
IEEE
15 years 10 months ago
Using Design Patterns to Overcome Image Processing Constraints on FPGAs
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resourc...
K. T. Gribbon, Donald G. Bailey, Christopher T. Jo...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
16 years 4 days ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...
FPL
2005
Springer
110views Hardware» more  FPL 2005»
16 years 1 days ago
CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
Robert G. Dimond, Oskar Mencer, Wayne Luk
ICCD
2007
IEEE
190views Hardware» more  ICCD 2007»
16 years 3 months ago
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
16 years 3 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...