Sciweavers

2945 search results - page 148 / 589
» Designing and Implementing Malicious Hardware
Sort
View
ICCAD
1997
IEEE
53views Hardware» more  ICCAD 1997»
15 years 10 months ago
A quantitative approach to functional debugging
We introduce a novel cut-based debugging paradigm. It coordinates design emulation and simulation and enables fast transition from one to another. Emulation or functional implemen...
Darko Kirovski, Miodrag Potkonjak
ICIP
1999
IEEE
16 years 8 months ago
Real Time Vector Median Like Filter FPGA Design and Application to Color Image Filtering
In this paper, the hardware implementation of a vector median like filter is proposed. Firstly, the extension of median filtering to the case of multicomponent images is addressed...
Jocelyn Chanussot, Michel Paindavoine, Patrick Lam...
ICCD
2002
IEEE
146views Hardware» more  ICCD 2002»
16 years 3 months ago
From ASIC to ASIP: The Next Design Discontinuity
A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a s...
Kurt Keutzer, Sharad Malik, A. Richard Newton
IISWC
2008
IEEE
16 years 28 days ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
TVLSI
2008
133views more  TVLSI 2008»
15 years 6 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias