2945 search results - page 131 / 589 » Designing and Implementing Malicious Hardware |
143
click to vote
DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
150
click to vote
ISLPED
1995
ACM
15 years 10 months ago
1995
ACM
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
163
click to vote
DATE
2008
IEEE
16 years 28 days ago
2008
IEEE
In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a syst...
151
click to vote
IWSOC
2005
IEEE
16 years 1 days ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
165
click to vote
VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...