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DSD
2009
IEEE
126views Hardware» more  DSD 2009»
15 years 10 months ago
Architecture-Driven Synthesis of Reconfigurable Cells
In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects...
Christophe Wolinski, Krzysztof Kuchcinski, Erwan R...
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
16 years 26 days ago
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
Mingjing Chen, Alex Orailoglu
IROS
2009
IEEE
186views Robotics» more  IROS 2009»
16 years 1 months ago
A design and analysis tool for underactuated compliant hands
— Highly underactuated and passively adaptive robotic hands have shown great promise for robust performance in unstructured settings. In order to fully realize this potential, ef...
Matei T. Ciocarlie, Peter K. Allen
CEC
2009
IEEE
16 years 1 months ago
Performance assessment of the hybrid Archive-based Micro Genetic Algorithm (AMGA) on the CEC09 test problems
— In this paper, the performance assessment of the hybrid Archive-based Micro Genetic Algorithm (AMGA) on a set of bound-constrained synthetic test problems is reported. The hybr...
Santosh Tiwari, Georges Fadel, Patrick Koch, Kalya...
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 3 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...