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ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
16 years 3 days ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
DAC
2000
ACM
16 years 7 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
TWC
2010
15 years 1 months ago
Optimal Linear Non-Regenerative Multi-Hop MIMO Relays with MMSE-DFE Receiver at the Destination
In this paper, we study multi-hop non-regenerative multiple-input multiple-output (MIMO) relay communications with any number of hops. We design the optimal source precoding matrix...
Yue Rong
IJACTAICIT
2010
84views more  IJACTAICIT 2010»
15 years 1 months ago
An Improved Deadlock Prevention Strategy for FMSs Using Theory of Regions
The theory of regions has been recognized as the optimal deadlock prevention policy based on the marking/transition-separation instance (MTSI) or the event-state-separation-proble...
Yi-Sheng Huang, Yen-Liang Pan
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
16 years 18 days ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky