The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
We are reaching a crisis with design of user interfaces for consumer electronics. Flashing 12:00 time indicators, push-andhold buttons, and interminable modes and menus are all sy...
We investigate the design of iterative, limited-precision mechanisms for single-good auctions with dominant strategy equilibria. Our aim is to design mechanisms that minimize the ...
In the so-called Information-Explosion Era, astronomical amount of information is ubiquitously produced and digitally stored. It is getting more and more convenient for cooperative...