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ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
15 years 10 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Structured Placement with Topological Regularity Evaluation
Abstract-- This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that plac...
Shigetoshi Nakatake
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, ...
DELTA
2004
IEEE
15 years 10 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 10 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt