4394 search results - page 632 / 879 » Designing agent chips |
193
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
160
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ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
– The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeas...
176
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
145
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-Â...
160
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MTDT
2003
IEEE
15 years 11 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...