Sciweavers

4394 search results - page 623 / 879
» Designing agent chips
Sort
View
IEEEPACT
2009
IEEE
16 years 1 months ago
DDCache: Decoupled and Delegable Cache Data and Metadata
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
ICVS
2009
Springer
16 years 1 months ago
Who's Counting? Real-Time Blackjack Monitoring for Card Counting Detection
This paper describes a computer vision system to detect card counters and dealer errors in a game of Blackjack from an overhead stereo camera. Card counting is becoming increasingl...
Krists Zutis, Jesse Hoey
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
16 years 1 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
DATE
2008
IEEE
130views Hardware» more  DATE 2008»
16 years 29 days ago
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs
—Increasing integrated circuit (IC) power densities and temperatures may hamper multiprocessor system-on-chip (MPSoC) use in hard real-time systems. This article formalizes the t...
Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 29 days ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek