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NOCS
2010
IEEE
15 years 4 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 4 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
PLDI
2011
ACM
14 years 9 months ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...
SIGSOFT
2005
ACM
16 years 7 months ago
Reasoning about confidentiality at requirements engineering time
Growing attention is being paid to application security at requirements engineering time. Confidentiality is a particular subclass of security concerns that requires sensitive inf...
Renaud De Landtsheer, Axel van Lamsweerde
ATAL
2009
Springer
16 years 1 months ago
Effective tag mechanisms for evolving cooperation
Certain observable features (tags), shared by a group of similar agents, can be used to signal intentions and can be effectively used to infer unobservable properties. Such infere...
Matthew Matlock, Sandip Sen