4394 search results - page 587 / 879 » Designing agent chips |
159
click to vote
ISLPED
2005
ACM
16 years 3 days ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
149
click to vote
CIS
2005
Springer
16 years 3 days ago
2005
Springer
⎯A new nonslicing floorplan representation, the moving block sequence (MBS), is proposed in this paper. Our idea of the MBS originates from the observation that placing blocks on...
202
click to vote
EMSOFT
2004
Springer
15 years 12 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
179
click to vote
GLVLSI
2003
IEEE
15 years 12 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
159
click to vote
ISPD
2003
ACM
15 years 11 months ago
2003
ACM
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...