Sciweavers

4394 search results - page 585 / 879
» Designing agent chips
Sort
View
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 27 days ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 27 days ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
GLOBECOM
2007
IEEE
16 years 27 days ago
Frequency Agile Interference-Aware Channel Sounding for Dynamic Spectrum Access Networks
— In this paper, we propose a novel channel sounding technique, called the multicarrier direct sequence swept time delay cross-correlation (MC-DS-STDCC), which is designed to min...
Qi Chen, Alexander M. Wyglinski, Gary J. Minden
VTC
2007
IEEE
101views Communications» more  VTC 2007»
16 years 25 days ago
Multi-Functional Antenna Array Assisted MC DS-CDMA Using Downlink Preprocessing Based on Singular Value Decomposition
—In this contribution we propose and investigate a transmitter preprocessing scheme designed for downlink transmission in multicarrier direct-sequence code-division multiple-acce...
Chong Xu, Bin Hu, Lie-Liang Yang, Lajos Hanzo
VTS
2007
IEEE
116views Hardware» more  VTS 2007»
16 years 25 days ago
Case Study: Soft Error Rate Analysis in Storage Systems
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
Brian Mullins, Hossein Asadi, Mehdi Baradaran Taho...