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NOCS
2009
IEEE
16 years 1 months ago
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...
Daniele Ludovici, Alessandro Strano, Davide Bertoz...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
16 years 1 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
CIKM
2009
Springer
16 years 1 months ago
Dynamic in-page logging for flash-aware B-tree index
This paper presents Dynamic IPL B+ -tree (d-IPL in short) as a B+ -tree index variant for flash-based storage systems. The d-IPL B+ -tree adopts a dynamic In-Page Logging (IPL) s...
Gap-Joo Na, Sang-Won Lee, Bongki Moon
DATE
2008
IEEE
142views Hardware» more  DATE 2008»
16 years 1 months ago
Developing Mesochronous Synchronizers to Enable 3D NoCs
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
Igor Loi, Federico Angiolini, Luca Benini
HPCA
2008
IEEE
16 years 1 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal