Sciweavers

4394 search results - page 551 / 879
» Designing agent chips
Sort
View
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
16 years 1 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
INFOCOM
2007
IEEE
16 years 28 days ago
TriBiCa: Trie Bitmap Content Analyzer for High-Speed Network Intrusion Detection
Abstract—Deep packet inspection (DPI) is often used in network intrusion detection and prevention systems (NIDPS), where incoming packet payloads are compared against known attac...
N. Sertac Artan, H. Jonathan Chao
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
16 years 20 days ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
IPPS
2006
IEEE
16 years 19 days ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
PPOPP
2005
ACM
16 years 5 days ago
Exposing speculative thread parallelism in SPEC2000
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...
Manohar K. Prabhu, Kunle Olukotun