4394 search results - page 540 / 879 » Designing agent chips |
157
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ANSS
2001
IEEE
15 years 10 months ago
2001
IEEE
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...
162
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
166
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
184
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FMCAD
2008
Springer
15 years 8 months ago
2008
Springer
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
166
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CAINE
2003
15 years 8 months ago
2003
Scan based or Line Sweep methods are a traditional mechanism to traverse the physical layout, or artwork of a microchip. These traversals are incremental in nature. They typically...