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DATE
2010
IEEE
118views Hardware» more  DATE 2010»
15 years 5 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung
DAC
2008
ACM
16 years 7 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem...
DAC
2008
ACM
16 years 7 months ago
Parallelizing CAD: a timely research agenda for EDA
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on paralle...
Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su
DAC
2002
ACM
16 years 7 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
DAC
2004
ACM
16 years 7 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...