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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
16 years 3 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
HPCA
2009
IEEE
16 years 1 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
ICDE
2009
IEEE
171views Database» more  ICDE 2009»
16 years 1 months ago
CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams
Applications involving analysis of data streams have gained significant popularity and importance. Frequency counting, frequent elements and top-k queries form a class of operato...
Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr ...
ICPP
2009
IEEE
16 years 1 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
16 years 1 days ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt