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CODES
2002
IEEE
15 years 11 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia
ISCAS
2002
IEEE
118views Hardware» more  ISCAS 2002»
15 years 11 months ago
A power-configurable bus for embedded systems
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
Chuanjun Zhang, Frank Vahid
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 11 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
15 years 11 months ago
Optimal regulation of traffic flows in networks-on-chip
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
ICCAD
1999
IEEE
98views Hardware» more  ICCAD 1999»
15 years 11 months ago
Buffer block planning for interconnect-driven floorplanning
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...
Jason Cong, Tianming Kong, David Zhigang Pan