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DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 12 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
15 years 12 months ago
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
Michael Nicolaidis, Nadir Achouri, Slimane Boutobz...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
15 years 12 months ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers
FDL
2003
IEEE
15 years 12 months ago
Dynamic Power Management of an AMBA-based Platform in SystemC
With System on Chip low power constraints becoming increasingly important, emphasis is moving to architectural level, optimum memory organisation and system run time management. T...
Massimo Conti, Marco Caldari, Simone Orcioni
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
15 years 12 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton