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IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
16 years 7 days ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
CHES
2005
Springer
80views Cryptology» more  CHES 2005»
16 years 6 days ago
Successfully Attacking Masked AES Hardware Implementations
During the last years, several masking schemes for AES have been proposed to secure hardware implementations against DPA attacks. In order to investigate the effectiveness of thes...
Stefan Mangard, Norbert Pramstaller, Elisabeth Osw...
FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
16 years 6 days ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
ICES
2005
Springer
121views Hardware» more  ICES 2005»
16 years 3 days ago
Hardware Platforms for MEMS Gyroscope Tuning Based on Evolutionary Computation Using Open-Loop and Closed-Loop Frequency Respons
Abstract. We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning met...
Didier Keymeulen, Michael I. Ferguson, Wolfgang Fi...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 12 months ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...