4394 search results - page 507 / 879 » Designing agent chips |
158
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
100
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, th...
191
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ETS
2007
IEEE
16 years 1 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
162
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IPPS
2007
IEEE
16 years 29 days ago
2007
IEEE
Supercomputers are increasingly complex systems merging conventional microprocessors with system on a chip level designs that provide the network interface and router. At Sandia N...
153
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IPPS
2007
IEEE
16 years 29 days ago
2007
IEEE
In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems...