System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lie...
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
Yi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan...