Sciweavers

4394 search results - page 504 / 879
» Designing agent chips
Sort
View
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 7 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
VLSID
2004
IEEE
142views VLSI» more  VLSID 2004»
16 years 7 months ago
Dynamic Noise Margin: Definitions and Model
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
Li Ding 0002, Pinaki Mazumder
ICCD
2007
IEEE
180views Hardware» more  ICCD 2007»
16 years 3 months ago
Improving the reliability of on-chip data caches under process variations
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lie...
ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
16 years 3 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
ICCAD
2008
IEEE
80views Hardware» more  ICCAD 2008»
16 years 3 months ago
Advancing supercomputer performance through interconnection topology synthesis
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
Yi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan...