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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
SPAA
2010
ACM
15 years 11 months ago
TLRW: return of the read-write lock
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
David Dice, Nir Shavit
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 11 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
BMCBI
2010
111views more  BMCBI 2010»
15 years 6 months ago
Dynamic probe selection for studying microbial transcriptome with high-density genomic tiling microarrays
Background: Current commercial high-density oligonucleotide microarrays can hold millions of probe spots on a single microscopic glass slide and are ideal for studying the transcr...
Hedda Høvik, Tsute Chen
COMPSAC
2005
IEEE
16 years 9 days ago
Exception Handling in Coordination-Based Mobile Environments
Mobile agent systems have many attractive features including asynchrony, openness, dynamicity and anonymity, which makes them indispensable in designing complex modern application...
Alexei Iliasov, Alexander B. Romanovsky