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ETS
2006
IEEE
118views Hardware» more  ETS 2006»
16 years 22 days ago
Living with Failure: Lessons from Nature?
- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continui...
Steve Furber
ISPASS
2005
IEEE
16 years 8 days ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...
CHES
2005
Springer
155views Cryptology» more  CHES 2005»
16 years 7 days ago
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse system...
Willi Geiselmann, Adi Shamir, Rainer Steinwandt, E...
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
16 years 3 days ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 11 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang