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RTAS
1997
IEEE
15 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
CASES
2008
ACM
15 years 8 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
16 years 1 months ago
An Organic Computing architecture for visual microprocessors based on Marching Pixels
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
Dietmar Fey, Marcus Komann, Frank Schurz, Andreas ...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
16 years 1 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
CEC
2005
IEEE
16 years 10 days ago
Evolving swarms that build 3D structures
The complex interactions of natural swarms, for example formed by some social insects, are difficult to comprehend. Considering tasks such as nestbuilding, the necessary underlyin...
Sebastian von Mammen, Christian Jacob, Gabriella K...