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GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
16 years 24 days ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
16 years 11 days ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
16 years 10 days ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
SLIP
2004
ACM
16 years 5 days ago
Optical solutions for system-level interconnect
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
Ian O'Connor
DAC
2010
ACM
15 years 10 months ago
An efficient algorithm to verify generalized false paths
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
Olivier Coudert